Verilog-Perl 3.482
- Released by
- WSNYDER
- Version
- Release Date
- 2024-01-23
- Kwalitee
- 131.25
- Core Kwalitee
- 90.62
- LINKS
Verilog-Perl 3.482 Latest
Kwalitee Issues
- buildtool_not_executable
-
Change the permissions of Build.PL/Makefile.PL to not-executable.
- has_license_in_source_file
-
Add =head1 LICENSE and the text of the license to the main module in your code.
- main_module_version_matches_dist_version
-
Make sure that the main module name and version are the same of the distribution.
- meta_yml_declares_perl_version
-
If you are using Build.PL define the {requires}{perl} = VERSION field. If you are using MakeMaker (Makefile.PL) you should upgrade ExtUtils::MakeMaker to 6.48 and use MIN_PERL_VERSION parameter. Perl::MinimumVersion can help you determine which version of Perl your module needs.
- has_meta_json
-
Add a META.json to the distribution. Your buildtool should be able to autogenerate it.
- proper_libs
-
Move your *.pm files in a directory named 'lib'. The directory structure should look like 'lib/Your/Module.pm' for a module named 'Your::Module'. If you need to provide additional files, e.g. for testing, that should not be considered for Kwalitee, then you should look at the 'provides' map in META.yml to limit the files scanned; or use the 'no_index' map to exclude parts of the distribution.
Error: EditFiles.pm, Getopt.pm, Language.pm, Netlist.pm, Netlist/Cell.pm, Netlist/ContAssign.pm, Netlist/Defparam.pm, Netlist/File.pm, Netlist/Interface.pm, Netlist/Logger.pm, Netlist/ModPort.pm, Netlist/Module.pm, Netlist/Net.pm, Netlist/Pin.pm, Netlist/PinSelection.pm, Netlist/Port.pm, Netlist/Subclass.pm, Parser/Parser.pm, Preproc/Preproc.pm, Parser/SigParser.pm, Std.pm
- has_known_license_in_source_file
-
Add =head1 LICENSE and/or the proper text of the well-known license to the main module in your code.
- use_warnings
-
Add 'use warnings' (or its equivalents) to all modules, or convince us that your favorite module is well-known enough and people can easily see the modules warn when something bad happens.
Error: Verilog::EditFiles, Verilog::Getopt, Verilog::Language, Verilog::Netlist, Verilog::Netlist::Cell, Verilog::Netlist::ContAssign, Verilog::Netlist::Defparam, Verilog::Netlist::File, Verilog::Netlist::Interface, Verilog::Netlist::Logger, Verilog::Netlist::ModPort, Verilog::Netlist::Module, Verilog::Netlist::Net, Verilog::Netlist::Pin, Verilog::Netlist::Port, Verilog::Netlist::Subclass, Verilog::Parser, Verilog::Preproc, Verilog::SigParser, Verilog::Std
- consistent_version
-
Split the distribution, or fix the version numbers to make them consistent (use the highest version number to avoid version downgrade).
Error: 3.427,3.482
- meta_yml_has_provides
-
Add all modules contained in this distribution to the META.yml field 'provides'. Module::Build or Dist::Zilla::Plugin::MetaProvides do this automatically for you.
- meta_yml_has_repository_resource
-
Add a 'repository' resource to the META.yml via 'meta_add' accessor (for Module::Build) or META_ADD parameter (for ExtUtils::MakeMaker).
Modules
| Name | Abstract | Version | View |
|---|---|---|---|
| Verilog::EditFiles | Split Verilog modules into separate files. | 3.482 | metacpan |
| Verilog::Getopt | Get Verilog command line options | 3.482 | metacpan |
| Verilog::Language | Verilog language utilities | 3.482 | metacpan |
| Verilog::Netlist | Verilog Netlist | 3.482 | metacpan |
| Verilog::Netlist::Cell | Instantiated cell within a Verilog Netlist | 3.482 | metacpan |
| Verilog::Netlist::ContAssign | ContAssign assignment | 3.482 | metacpan |
| Verilog::Netlist::Defparam | Defparam assignment | 3.482 | metacpan |
| Verilog::Netlist::File | File containing Verilog code | 3.482 | metacpan |
| Verilog::Netlist::Interface | Interface within a Verilog Netlist | 3.482 | metacpan |
| Verilog::Netlist::Logger | Error collection and reporting | 3.482 | metacpan |
| Verilog::Netlist::ModPort | ModPort within a Verilog Interface | 3.482 | metacpan |
| Verilog::Netlist::Module | Module within a Verilog Netlist | 3.482 | metacpan |
| Verilog::Netlist::Net | Net for a Verilog Module | 3.482 | metacpan |
| Verilog::Netlist::Pin | Pin on a Verilog Cell | 3.482 | metacpan |
| Verilog::Netlist::PinSelection | Nets attached to a Verilog Cell's Pins | 3.427 | metacpan |
| Verilog::Netlist::Port | Port for a Verilog Module | 3.482 | metacpan |
| Verilog::Netlist::Subclass | Common routines for all classes | 3.482 | metacpan |
| Verilog::Parser | Parse Verilog language files | 3.482 | metacpan |
| Verilog::Preproc | Preprocess Verilog files | 3.482 | metacpan |
| Verilog::SigParser | Signal Parsing for Verilog language files | 3.482 | metacpan |
| Verilog::Std | SystemVerilog Built-in std Package Definition | 3.482 | metacpan |